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fn6428 rev 1.00 page 1 of 20 april 2, 2007 fn6428 rev 1.00 april 2, 2007 isl97801 high power led driver datasheet the isl97801 is a high-power led backlight driver with an integrated 36v fet designed to drive up to 8 high-power leds in series. the pwm convert er runs from an internally generated 1mhz clock. with efficiencies over 90% the regulator provides tight cont rol of led current and may be configured in either boost or buck topologies, allowing from 3 to 8 series diodes to be drive n from wide input voltages. led light level may be controlled either by: 1. led dc bias current set via the level pin, or 2. external low frequen cy pwm control via the enable/pwm pin. in both control mo des optional over temperature thermal protection of the led reduc es the led dc bias current above an adjustable set temper ature, protect ing the led from thermal damage. an optiona l fault monitor drives an external fet between the i nput supply and inductor, providing short circuit current protection for the led and inductor as well as load dump protection for automotive applications. for low cost app lications the pass transistor may be omitted and t he fault pin bypassed. the isl97801 is packaged i n a 20 ld 4mm x 4mm qfn package and is specif ied for operation over the -40c to +105c temper ature range. features ? drives 3-8 high-power le ds in series, up to 32v ? 2.7v to 16v input voltage range ? boost or buck configurable switch ? 3a integrated fet ? automotive load dump protection ? light output tempe rature compensation ? led over-temperature protection ? led disconnect ? pwm/analog light level control ? small, 20 ld 4mm x 4mm qfn package ? pb-free plus anneal available (rohs compliant) applications ? display backlighting - automotive - lcd monitor - notebook displays ? led accent lighting ? automotive lighting pinout isl97801 (20 ld 4x4 qfn) top view ordering information part number (note) part marking tape & reel/ qty package (pb-free) pkg. dwg. # ISL97801ARZ 978 01arz - 20 ld 4x4 qfn l20.4x4c ISL97801ARZ-tk 978 01arz 13/ 1,000 20 ld 4x4 qfn l20.4x4c ISL97801ARZ-t 978 01arz 13/ 6,000 20 ld 4x4 qfn l20.4x4c note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/d ie attach materials and 100% matte tin plate termination finish, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 2 3 4 15 14 13 12 6 7 8 9 20 19 18 17 vdc vhi ovp swd1 b uck/boostn level temp fb vin fault gnd nc enl mode en/pwm sws1 thermal pad 5 swd2 10 tmax 11 sws2 16 vbat not recommended for new designs recommended replacement part isl97634
isl97801 fn6428 rev 1.00 page 2 of 20 april 2, 2007 absolute maximum ratings (t a = +25c) thermal information maximum pin voltage, all pins except below 6.5v v in, sws1, sws2, en/pwm . . . . . . . . . . . . . . . . . . . . . . . . . . .18v vbat, fault, fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24v |vhi - sws1, sws2| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v swd1, swd2, ovp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1a operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c thermal resistance ? ja (c/w) / ? jc (c/w) qfn-20 package (notes 1, 2) . . . . . . . 39 2.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a operating continuously at a junction temperature of +135c will shorten the life of the device while the thermal shutdown may t rigger at a higher temperature than +135c since it is a typical number. note: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications v bat = v in = 12v, v dc = 5v, t a = -40c to +105c unless otherwise specified. parameter description conditions min typ max unit vin input supply voltage i out = 350ma, 8 leds, buck/boostn = gnd 516v vin input supply voltage i out = 350ma, 5 leds, buck/boostn = gnd, tmax disabled 2.7 12 v v bat input supply monitor normal operating range 2.7 16 v v batfault supply fault threshold if v bat > v batfault , fault pin is switched to ground 17.6 21 24 v i s e n supply current in v in no switching, en/pwm = 1 2.7 3.5 ma i s d is supply current in v in no switching, en/pwm = 0 0.6 2.5 a r switch power fet on resistance i switch = 600ma 0.15 0.25 ? v dc regulated auxiliary supply 4.75 5 5.25 v r outol auxiliary supply open loop output resistance v in < v dc 40 ? r outcl auxiliary supply closed loop output resistance v in > 6v, f < 100hz 6.5 ? i out output drive current 4 led output string. v in = v bat = 10v 1 a i limboost power switch current limit buck/boostn = gnd 3.6 a i limbuck power switch current limit buck/boostn = vdc 2.4 a ovph over voltage positive going voltage mode threshold upper threshold to enter overvoltage fault mode, t a = +25c 31 32 v ovpl over voltage negative going voltage mode threshold lower threshold to exit overvoltage fault mode, t a = +25c 20 23 v v gate protection fet vgs (gate clamp) v in - v fault 9.76 12.2 14.64 v v gate protection fet vgs (gate clamp) v fault - v in 8.16 10.2 12.24 v v fb feedback voltage system in regulation, v level = 1v, vin = 12v, 6 leds 0.19 0.2 0.21 v
isl97801 fn6428 rev 1.00 page 3 of 20 april 2, 2007 . v level light control voltage linear input range mode = 1, analog contro l of led current 0.25 3 v fb uv fault feedback undervoltage fault vlevel = 1v, en/pwm = 3v 120 160 180 mv fb ov fault feedback overvoltage fault vlevel = 1v, en/pwm = 3v 220 250 280 mv f sw switching frequency 850 1000 1150 khz f dimming maximum recommended pwm dimming frequency mode = 1, modulation signal applied to en/pwm 10 khz t switch load switch transition time c gate = 2nf 100 ns rls driverl load switch driver impedance low en/pwm = 0 30 50 ? rls driverh load switch driver impedance high en/pwm = 3v 30 50 ? t fault fault timer period 40 50 58 ms t delay start-up delay timed lx switching delay 0.85 1 1.17 ms v faultpump fault pin charge pump v bat = v in = 3v 6 v v boost boost mode threshold buck/boostn = gnd 0.4v dc v v buck buck mode threshold buck/boostn = v dc 0.94v dc v v model mode low threshold mode = gnd 1/3v dc v v modeh mode high threshold mode = v dc 2/3v dc v en fault input level applied to tmax pin to enable fault protection 0.9v dc v dis fault input level applied to tmax pin to disable fault protection 0.96v dc v en temp input level applied to temp pin to enable temperature compensation 0.5 v dis temp input level applied to temp pin to disable temperature compensation 0.08 v t compp vfb positive temperature compensation; vfb/vfbnom vtemp/vdc = 0.80 1.26 t compn vfb negative temperature compensation; vfb/vfbnom vtemp/vdc = 0.20 0.74 t trip internal temperature protection threshold 135 c t hys internal temperature protection hysteresis 25 c ven/pwm l en/pwm pin input low threshold 1.2 v ven/pwm h en/pwm pin input high threshold 2.5 v v dcuvlo v dc under voltage lockout 2.6 v rschottky internal schottky diode for buck 15 23 ? electrical specifications v bat = v in = 12v, v dc = 5v, t a = -40c to +105c unless otherwise specified. (continued) parameter description conditions min typ max unit table 1. light output control, v dc = 5.0v mode temp operating mode 1 (vdc - 0.25) > v > 0.25v standard mode light level to pwm modulation of en/pwm input; led bias curren t determined by level voltage, nominal 1v dont care v < 0.25v disable temperature compensation 0 v < (vdc - 0.25) fixed bias mode v fb level internally set to 0.4v, independent of v level
isl97801 fn6428 rev 1.00 page 4 of 20 april 2, 2007 typical performance curves figure 1. 8 leds efficiency vs input voltage vs dimming frequency and duty cycle figure 2. 5 leds efficiency vs input voltage vs dimming frequency and duty cycle figure 3. 3 leds efficiency vs input voltage vs dimming frequency and duty cycle figure 4. 8 and 5 leds efficiency vs pwm duty cycle figure 5. leds pwm dimming linearity figure 6. 8 leds current accu racy vs input voltage 60 65 70 75 80 85 90 95 100 6 8 10 12 14 16 18 v in (v) efficiency (%) 8 leds i ledpeak = 380ma 10%@100hz 10%@10khz 99%@100hz 99%@10khz 50%@1khz 50%@10khz 50%@100hz 10%@1khz 99%@1khz 60 65 70 75 80 85 90 95 100 4 6 8 10121416 v in (v) efficiency (%) 5 leds i ledpeak = 380ma 99% @ 10khz 99% @ 100hz 10% @ 10khz 10% @ 100hz 60 65 70 75 80 85 90 95 100 4810 v in (v) efficiency (%) 3 leds i ledpeak = 380ma 6 99%@100hz 99%@10khz 10%@10khz 10%@100hz 60 65 70 75 80 85 90 95 100 0 20406080100 pwm dimming duty cycle (%) efficiency (%) 8 leds 5 leds i ledpeak = 380ma pwm = 10khz 8 leds, v in = 12v 5 leds, v in = 9v 0 50 100 150 200 250 300 350 400 0 20406080100 pwm dimming duty cycle (%) i led (ma) 8 leds, v in = 12v i ledpeak = 380ma 5 leds @ 100hz 5 leds, v in = 9v 3 leds, v in = 5v 3 leds @ 100hz 8 leds @ 1khz 5 leds @ 10khz 8 leds @ 10khz -6 -5 -4 -3 -2 -1 0 1 2 3 4 6 8 10 12 14 16 18 v in (v) ? i led (%) 8 leds i ledpeak = 380ma 10% @ 100hz 99% @ 100hz 99% @ 10khz 10% @ 10khz
isl97801 fn6428 rev 1.00 page 5 of 20 april 2, 2007 figure 7. 5 leds current accuracy vs input voltage figure 8. 3 led s current accuracy vs input voltage figure 9. 8 leds line regulation of pwm duty cycle of 99% figure 10. 5 leds line regulation of pwm duty cycle of 99% figure 11. 3 leds line regulation of pwm duty cycle of 99% figure 12. 8 leds line regulation of pwm duty cycle of 10% typical performance curves (continued) -10 -8 -6 -4 -2 0 2 4 6 8 10 4 6 8 10 12 14 16 v in (v) ? i led (%) 5 leds i ledpeak = 380ma 10% @ 100hz 10% @ 10khz 99% @ 100hz 99% @ 10khz -4 -2 0 2 4 6 8 10 12 14 16 10 9 8 7 6 5 4 v in (v) ? i led (%) 3 leds i ledpeak = 380ma 99% @ 100hz 99% @ 10khz 350 355 360 365 370 375 380 385 390 395 400 6 8 10 12 14 16 18 v in (v) i led (ma) 8 leds i ledpeak = 380ma pwm @ 100hz pwm @ 10khz duty cycle = 99% pwm @ 1khz 350 355 360 365 370 375 380 385 390 395 400 405 410 415 420 4 6 8 10 12 14 16 i led (ma) v in (v) 5 leds i ledpeak = 380ma 99% @ 100hz duty cycle = 99% 99% @ 10khz 360 365 370 375 380 385 390 395 400 405 410 4567 8910 i led (ma) 3 leds i ledpeak = 380ma pwm @ 100hz duty cycle = 99% pwm @ 10khz v in (v) 30 31 32 33 34 35 36 37 38 39 40 6 8 10 12 14 16 18 i led (ma) 8 leds i ledpeak = 380ma duty cycle = 10% pwm @ 10khz v in (v) pwm @ 100hz pwm @ 1khz
isl97801 fn6428 rev 1.00 page 6 of 20 april 2, 2007 figure 13. 5 leds line regulation of pwm duty cycle of 10% figure 14. 3 leds line regulation of pwm duty cycle of 10% figure 15. led current vs v level bias figure 16. quiescent current (non-switching) figure 17. start-up waveforms figu re 18. start-up waveforms zoom-i n typical performance curves (continued) 34 35 36 37 38 39 40 41 6 8 10 12 14 16 18 i led (ma) v in (v) 10% @ 100hz 10% @ 10khz 5 leds i ledpeak = 380ma duty cycle = 10% 32 33 34 35 36 37 38 39 40 41 42 4567 8910 i led (ma) v in (v) 3 leds i ledpeak = 380ma duty cycle = 10% pwm @ 10khz pwm @ 100hz 0 50 100 150 200 250 300 350 400 0 0.2 0.4 0.6 0.8 1.0 v level (v) i led (ma) rset = 0.5 ? duty cycle = 100% 5 led 3 led 8 led 0.0001 0.001 0.01 0.1 6 8 10 12 14 16 18 v in (v) i q (ma) en/pwm = 0 v level = 1v t a = +25c 8 leds i led = 350ma 8 leds i led = 350ma
isl97801 fn6428 rev 1.00 page 7 of 20 april 2, 2007 figure 19. 50% pwm dimming at 100hz figure 20. 50% pwm dimming at 10khz figure 21. 10% pwm dimming at 1khz figure 22. 50% pwm dimming at 1 khz zoom-in figure 23. transient response operates from 8 to 7 leds figure 24. transient response operates from 7 to 8 leds typical performance curves (continued) 8 leds v in = 16v pwm = 100hz 8 leds v in = 16v pwm = 10khz 8 leds v in = 12v pwm = 1khz pwm = 1khz duty cycle = 50% 8 leds v in = 16v transient response when load dynamically v in = 12v i led = 350ma changes from 8 leds to 7 leds 8 leds v o 7 leds v o transient response when load dynamically v in = 12v i led = 350ma changes from 7leds to 8leds 7 leds v o 8 leds v o
isl97801 fn6428 rev 1.00 page 8 of 20 april 2, 2007 typical boost mode application diagram figure 25. ovp and reset figure 26. current limit typical performance curves (continued) fb = 0v 8leds v in = 3.3v i led = 380ma 9+, 6:' 6:' 293 6:6 6:6 (1/ *1' 9,1 )$8/7 9%$7 9'& %8&.%22671 7(03 70$; (13:0 02'( /(9(/ 9 %$7 9 '& ?) 3:0 9 )% ),*85( 7<3,&$/%226702'($33/,&$7,21&,5&8,7 7(03 6(1625
isl97801 fn6428 rev 1.00 page 9 of 20 april 2, 2007 pin descriptions pin name description 1 vdc internally regulated 5v supply, tracks v in for input voltages less than 5v . ldo output can also be biased with external supply if vin is <5.5v . a minimum of 3.3f decoupling capacitor is needed in this pin. 2 vhi power fet gate drive supply. can be biased with external su pply if vin is <5.5v 3 ovp overvoltage monitor input; tie to vout for normal operation 4 swd1 nmos power fet drain 5 swd2 nmos power fet drain 6 buck/boostn tie to gnd for boost operation and to vdc for buck operation 7 level sets led bias current l evel; vfb(nominal) = vlevel/5 8 temp temperature reference, tie to gnd to disable temperature c ompensation 9 fb led current feedback 10 tmax maximum led temperature set point; if temp voltage exceed s tmax, fb set point will be reduced 11 sws2 nmos power fet source 12 sws1 nmos power fet source 13 en/pwm chip enable and light m odulation pwm dimming input 14 mode digital input; tie to gnd to set fb reference to 400mv, t ie to vdc to control fb reference with level input 15 enl led load isola tion mos gate driver 16 vbat input supply monitor 17 nc leave floating (internally connected) 18 gnd ground return and fb ground reference 19 fault gate drive of fault protection fet. driven low under fau lt conditions 20 vin input supply
fn6428 rev 1.00 page 10 of 20 april 2, 2007 isl97801 functional block diagram start-up charge pump fault control and timer ldo and ref clock and ramp generator inner loop pwm control and current limit load current sense temperature compensation mode control light control por v dc ref gnd level mode en/pwm buck/ boostn halt en o/p v start 2.7v-16v vbat fault vin vdc vhi swd1 sws1 enl fb l halt v start ref clk r amp v dc en o/p fet current sense clk r amp halt level (t) temp tmax isl97801 sws2 figure 28. isl97801 block diagram ovp swd2
isl97801 fn6428 rev 1.00 page 11 of 20 april 2, 2007 theory of operation general description the isl97801 is a flexible, hig hly integrated high-power led driver consisting of a pwm switch ing controller an d integrated 36v ndmos power fet. the devi ce can drive u p to 8 series high-power led's at currents u p to 1a at 16v input or 5 leds at current up to 350ma at 2.7v input. the control loop can be configured as either as a boost or buck regulator with the configuration of the buck/boos tn pin, providing an output voltage above or below the input supply voltage, depending on the number of stacked led's. t he controller operates from 2.7v to 16v depending on the numbers of leds and current required and can be powered by a single lithium ion battery, 5v or 12v regulated supplie s or automotive electrical systems. led current is sensed through a low value resistor in series with the led. a thermistor can be used to implement a thermal protection scheme to limit the maximum led temperature to a preset desirable level. switching regulator the isl97801 employs a curr ent mode pwm control scheme with a nominal switching frequency of 1mhz. this provides fast transient response and enables the use of low profile inductors and compact multilayer ceramic capacitors. settling time is optimized by the use of a simpl e control loop without an error amplifier, relying instead on in trinsic gain within the direct summing path. due to the lower loop gain, offset must be accounted for when setting up initial led bias current. refer t o the applications section of the datasheet for further information. figure 28 shows a block di agram of the system. application configurations operating modes the isl97801 can operate as either a buck or boost regulator. hardwire buck/boostn to gnd for boost mode or to vdc for buck mode. in buck mode the power ndmos drive circuit is "floated" (boot-strapped) al lowing the ndmos gate to be driven above vin to fully enh ance the power ndmos. an internal schottky diode betwe en vdc (5v) and vhi reduces external component count. use a c eramic capacitor of at least 50nf between vhi and sws1/2 to bootstrap vhi. led load connection isl97801 includes an auto-sensing fb level shift circuit that enables the led load to be co nnected to either gnd or vin. an internal sense circuit monitors the fb pin voltage. when the level exceeds vdc/2, the feed back reference voltage is switched from gnd to vin. refer to the application section of the datasheet for typical application schematics. start-up to maximize external pwm s witching speed, the isl97801 does not include an internal soft-start circuit. when vdc exceeds the power on reset threshold, switching is delayed for 1ms (t delay ) allowing the output capac itor to charge through the inductor. if soft-start cont rol is required, a suitable application circuit is shown in figure 30. light level control two light control schemes are provided: 1. an external pwm signal via the en/pwm pin, providing low frequency pwm dimming. 2. bias current level adjustm ent via the level input or fixed internal bias. pwm dimming led color temperature varies with bias current. in backlighting applications pwm dimming offe rs better control of color temperature because current through the led's is kept constant. a 5v gate driver (enl) synchronized to en/pwm can be used to control an exter nal n-ch fet and disconnect the led stack during the pwm off period. the switch prevents discharge of the output capacitor by the led load, maintaining a constant bias independent of pwm duty cycle. operation at 1khz pwm rate is shown in figure 31 and figure 32. the load disconnect switch improves pwm dynamic range, linearity and color temperature control. to further improve the linearity of r s e n s e 0 . 5 level shift el 7 8 0 1 gnd vin fb + - vo l t ag e fe e db ac k vdc / 2 figure 29. fb reference auto switch figure 30. external soft-start circuit cout 20f r1 100 vin fb sws1 sws2 swd1 swd2 vbat fault isl97801 vbat vout c1 4.7nf r2 2k l1 10h rsense 0.5
isl97801 fn6428 rev 1.00 page 12 of 20 april 2, 2007 pwm dimming, an internal tim er delays system shutdown via en/pwm for 50ms. bias current dimming current in the led load is de termined by the value of the feedback resistor and the target feedback regulation voltage: with mode tied to vdc, voltage across the feedback resistor is set by v level : the value of v fb should be limited t o between 50mv and 450mv for linear operation. for minimum light output, v fb may be set below 50mv. with mode tied to gnd, voltage across the feedback resistor is set at ~400mv via an internal reference. in either operating mode, if led temperature control is enabled the value of vfb will be reduced when maximum led temperature is exceeded. input overvoltage for automotive applications, an external high voltage nfet driven by the fault pin disconn ects the device from the input supply in response to voltage spikes on the input supply. during start-up an internal cha rge pump drives the fault pin above the input voltage, ensu ring the nfet is fully enhanced and powering up the device. in normal operation the switching node of the boost regulator or the floating supply of the buck regulator is used to pump faul t above vin. on detection of an overvoltage, the fault pin is discharged to gnd. the gate to source voltage of the ndmos is internally limited to 15v to prevent voltage stress. fault protection the external nfet is also used a s a fault protection switch, disconnecting the input supply if a fault occurs for more than 50ms. the system monitors f eedback voltage r egulation, output overvoltage and input over voltage. for applications not requiring input voltage or faul t protection, connect vbat and vin directly together. all faults except input supply overvolta ge latch the isl97801 in to an off state that can be cleared by either power cycling the input supply or the en/pwm pin. connecting the tmax pin to v dc disables the fault latch function (led over temperatur e control is also disabled). output overvoltage protection (ovp) if the fb pin is shorted to gr ound or an led fails open circui t, output voltage in boost mode can increase to potentially damaging voltages. an optional overvoltage protection circuit can be enabled by conn ection of the ovp pi n to the output voltage. the device will stop s witching if the output voltage exceeds ovph and re-start wh en the output voltage falls below ovpl. during sustained ovp fault conditions, v out will saw-tooth between the upper and lower threshold voltages at a frequency determined by the magn itude of current available to discharge the outpu t capacitor and th e value of output capacitor used. the ovp threshold can be set to a lower value by using an external zener diode and resisto r, as shown in figure 33. r1 should be adjusted to minimize of fset in the fb voltage due to fb pin input current. a value of 100 ? is recommended. figure 31. operation with enl controlled fet figure 32. operation with no enl controlled fet i led v fb r sense ----------------------- = (eq. 1) v fb v level 5 --------------------- - = (eq. 2)
isl97801 fn6428 rev 1.00 page 13 of 20 april 2, 2007 over temperature shutdown an internal sense circuit disab les pwm switchi ng if the die temperature exceeds +135c. switching is re-enabled when the temperat ure falls below +100c. internal 5v ldo an internal ldo between vin and vdc regulat es vdc to 5v, to power control an d gate drive circui ts when vin exceeds 5.1v. in normal operation decoupl e vdc with at least 3.3f. in applications where the input su pply is less than 5.5v, vdc should be tied directly to vin. led temperature control led lifetime reduces dramatically with el evated temperature. an over temperature control circuit utiliz ing the thermistor voltage at temp reduces the le d bias current when vtemp exceeds the threshold voltage on tmax. to minimize noise injection use a potential divid er between vdc and gnd to set the voltage on tmax, as shown in figure 34. the value of tmax for a specific threshold te mperature is determined by the choice of thermistor temperature coefficient. disable the function by connecting the tmax pin to vdc and temp pin to gnd . component selection input capacitor switching regulators require input capacit ors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interacti on between the regulator and input supply, improvi ng system stability. t he high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. considerably more input curren t ripple is generated in buck mode than boost mode. in bu ck mode input current is alternately swit ched between i out and zero. the rms current flow in the input cap acitor is given by: where: d = duty cycle the input current is maximu m for d = 0.5 and when i out approaches current limit (2.4a) giving a value of around 1.2a. a capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic caps. in boost mode input current fl ows continuously into the inductor, with an ac ripple com ponent proportional to the rate of inductor charging only and sma ller value input capacitors may be used. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. in automotive applications the i nput capacitor can be protected from exposure to high voltages p resent during fault conditions (load dump) by connecting it downstream of the fault protection switch, as shown in figures 39 and 40. inductor careful selection of inductor value will optimise circuit operation. inductor type and value influence many key parameters, including ripple cu rrent, current limit, efficiency , transient performance and stability. internal slope compensation has been optimised for inductor values between 4.7h and 10h. ensure the induct or current rating is capable of handling the current limit val ue in the configuration used (2.4a for buck, 3.5a for boost). i f an inductor core is chosen with too low a current rating, s aturation in the core will caus e the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. figure 33. external ovp circuit cout 20f r1 100 vin fb sws1 sws2 swd1 swd2 vbat fault isl97801 vbat zovp vout l1 10h 0.5 rsense r s e n s e 0 . 5 el 7 8 0 1 g nd vin temp thermistor close to leds vdc ldo creg 0.47uf rm1 20k rt 10k + - temp co m p e n s a t i o n rm2 80k tmax fb level adust current figure 34. over-temperature circuit i caprms i out dd 2 C ?? ? = (eq. 3)
isl97801 fn6428 rev 1.00 page 14 of 20 april 2, 2007 rectifier diode a high speed rectifier diode is n ecessary to prevent excessive voltage overshoot, especially in the boost configuration. low forward voltage and reverse le akage current will minimize losses, making schottky diodes t he preferred choice. similarly to the inductor, a diode with a suitable current rating to hand le current limit in the conf iguration must be used. output capacitor the output capacitor acts to smo oth the output v oltage and in the boost configuaration supplie s load current directly during the conduction phase of the power switc h. ripple voltage consists of two components, t he first due to charging and discharging of the capacitor; the second due to ir drop across the esr of the capacitor by inductor ripple current. in boost mode: where: and in buck mode: where: for a low esr ceramic capacitor, output ripple is dominated by the charging and disc harging of the output capacitor. care should be taken to ensure the vo ltage rating of t he capacitor exceeds the maximu m output voltage. compensation the isl97801 employs a dire ct summing control loop with current feedback. no error amplif ier is used in the system. the arrangement provides fast tra nsient response and makes use of the output capacitor to comp ensate the loop. the effect of the pole associated with the inductor is minimized by the current feedback. the number o f leds, their dc bias current and the value of feedback resisto r alter loop stability due to their effect on feedba ck factor which is hea vily influenced by the small signal impedance of the leds. generally, higher numbers of leds, lower bias le vels and smaller values of feedback resistor will require s maller output capacitors to achieve loop stability. a combi nation of low esr electrolytic and ceramic capacitors may be used to reduce implementation costs. v ripple i o c out --------------- - d f s ------ - ? i lpk esr ? + = (eq. 4) d v out v in C v out ------------------------------- - = (eq. 5) i lpk i o 1d C ------------- v out v in C ?? 2l ? ------------------------------------ + 1d C ?? f s ------------------ ? = (eq. 6) v ripple v in v out C ?? d ? 2f s ? l ? ---------------------------------------------- - d f s c out ? -------------------------- - esr + ?? ?? ? = (eq. 7) d v out v in --------------- - = (eq. 8) table 2. boost mode compensation. 2.7v operation vfb i out vout (v) 7 10.5 14 17.5 21 24.5 28 leds2345678 50mv 50ma electrolytic 94f 47f dmax dmax ceramic 40f 20f 40f 20f 20f 100mv 100ma electrolytic 94f ceramic 60f 60f 40f 40f 40f 200mv 350ma electrolytic 94f 47f 47f 47f ilim ilim ilim ceramic 60f 40f 40f 40f 200mv 1a electrolytic ilim ilim ilim ilim ilim ilim ilim ceramic table 3. boost mode compensation 6v operation vfb i out vout (v) 7 10.5 14 17.5 21 24.5 28 leds2345678 50mv 50ma electrolytic 94f 47f ceramic 40f 20f 40f 20f 20f 20f 20f 100mv 100ma electrolytic 141f 47f ceramic 60f 60f 60f 40f 40f 40f 40f 200mv 350ma electrolytic 141f 47f 47f ceramic 60f 60f 40f 60f 40f 40f 40f 200mv 1a electrolytic 94f 47f ilim ilim ilim ilim ilim ceramic 40f 40f
isl97801 fn6428 rev 1.00 page 15 of 20 april 2, 2007 a note about ceramic capacitors: many ceramic capacitors have s trong voltage and temperature coefficients which reduces effective capacitance as the applied voltage or operating temperatur e is increased. pay careful attention when selecting ceramic capacitor type. x5r and x7r families provide much better st ability than y5v, which should generally be avoided unless additional capacitance is added to compensate for the significant changes in value which occurs over voltage a nd temperature. layout considerations pcb layout is very important for the converter to function properly. the following general g uidelines should be followed: ? separate the power ground and signal ground; connect them only at o ne point close to the gnd pin. ? maximize the power ground area as much as possible. it is essential to ensure th power ground return between cin, cout, and sws1,2 as leas t obstructive as possible. ? place the input capacitor clos e to vin and sws1,2 pins in boost mode. ? make the following pc traces as short as possible: - from swd1,2 to the inductor in boost mode - from sws1,2 to the inductor in buck mode - from cout to pgnd ? feedback signals levels are small to improve efficiency. ensure the reference connect ion (gnd or vin) between the sense resistor and i c pin doesn't carry switching current. ? place several via holes (the rmal vias) under t he chip to a backside ground plane to i mprove heat dissipation ? maximize the copper area around the thermal vias to spread heat away from the chip. cost-sensitive applications for cost-sensitive applicati ons, the bom can be reduced considerably by: 1. removing temperature compensation 2. removing the faul t-protection switch 3. removing the load isolation switch 4. switching the fb into inte rnal fixed bias mode (400mv across v fb ) in this configuration, light lev el may be contro lled using the en/pwm input to modulate the output current. in the absence of the load isolat ion switch, led bias current will vary with pwm dut y cycle, due to the discharge of the output capacitor by the leds during the pwm off time therefore low dimming frequencie s can only be used in such application. table 4. boost mode compensation 12v operation vfb i out vout (v) 7 10.5 14 17.5 21 24.5 28 leds2345678 50mv 50ma electrolytic ceramic dmin dmin dmin 60f 40f 40f 40f 100mv 100ma electrolytic 47f 47f ceramic dmin dmin dmin 40f 20f 40f 40f 200mv 350ma electrolytic 47f 47f ceramic dmin dmin dmin 40f 20f 40f 40f 200mv 1a electrolytic 47f 47f ceramic dmin dmin dmin 20f 20f 40f 40f table 5. ceramic capacitor variability capacitor type typical voltage variation temperature variation x7r, 10v -30% at 10v -15% at +125c x5r, 25v -50% at 25v -9% at +85c y5v, 6.3v -90% at 6.3v -65% at +85c
isl97801 fn6428 rev 1.00 page 16 of 20 april 2, 2007 boost mode appl ication diagram boost mode with over current faul t and led temperat ure protections application diagram vin fault vbat vdc temp tmax en/pwm mode level buck/boostn vhi swd1 swd2 sws1 sws2 enl fb gnd en v bat ovp figure 35. basic boost application circuit vin fault vbat vdc temp tmax en/pwm mode level buck/boostn vhi swd1 swd2 sws1 sws2 enl fb gnd temp sensor en v level (0v to 2.5v) v bat ovp figure 36. boost mode application with over current fault protec tion and led temperature protection
isl97801 fn6428 rev 1.00 page 17 of 20 april 2, 2007 typical buck application diagram buck mode with over current fault and led temperature protections application diagram vin fault vbat vdc temp tmax en/pwm mode level buck/boostn vhi swd1 swd2 sws1 sws2 enl fb gnd en v bat ovp figure 37. basic buck application circuit vin fault vbat vdc temp tmax en/pwm mode level buck/boostn vhi swd1 swd2 sws1 sws2 enl fb gnd temp sensor en v level (0v to 2.5v) v bat ovp figure 38. buck mode with over current fault and led temperature protections application
isl97801 fn6428 rev 1.00 page 18 of 20 april 2, 2007 automotive applications the led load and is l97801 may be protected against load dumps and other electrical faul ts in automotive supplies with a minor addition to the stan dard application schematic: ? a reverse transient automot ive-rated protection power schottky must be added in s eries with the input supply ?a 500 ? current limit resistor must be inserted in series with the v bat pin ? the fault protection nfet must be specified to handle 100v vds conditions. the protection circuit is applicable to buck, boost, and supply-return load applications. a small reduction in efficiency is caused by t he drop in the power schottky. unless alternative transient pro tection is provided, minimum bom automotive applications must include the circuit changes noted above. automotive boost application diagram automotive minimum bom b oost application diagram vin fault vbat vdc temp tmax en/pwm mode level buck/boostn vhi swd1 swd2 sws1 sws2 enl fb gnd temp sensor en v level (0v to 2.5v) v bat ovp r lim 500 figure 39. automotive boost mode application diagram vin fault vbat vdc temp tmax en/pwm mode level buck/boostn vhi swd1 swd2 sws1 sws2 enl fb gnd en v level (0v to 2.5v) v bat ovp figure 40. automotive minimum bom boost mode application
fn6428 rev 1.00 page 19 of 20 april 2, 2007 isl97801 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2007. all rights reserved. all trademarks and registered trademarks are the property of their respective owners.
isl97801 fn6428 rev 1.00 page 20 of 20 april 2, 2007 package outline drawing l20.4x4c 20 lead quad flat no-lead plastic package rev 0, 11/06 located within the zone indicate d. the pin #1 indentifier may b e unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommen ded land pattern top view bottom view side view 4.00 a 4.00 b 6 pin 1 index area (4x) 0.15 4x 0.50 2.0 16x 20 16 15 11 pin #1 index area 6 2 .70 0 . 15 5 1 20x 0.25 +0.05 / -0.07 0.10 m ab c 20x 0.4 0.10 4 6 10 base plane seating plane 0.10 see detail "x" 0.08 c c c 0 . 90 0 . 1 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 8 typ ) ( 2. 70 ) ( 20x 0 . 6) ( 20x 0 . 5 ) ( 20x 0 . 25 )

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